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features ? ldo1: 2.75v (default) and 1.8v (programmabl e by twi), 70 ma linear very low drop out regulator with high psrr and low noise. ldo2: 1.8v (default) and 1.5v (programma ble by twi), 70 ma linear low drop out regulator with high psrr and low noise. ldo3: 1.8v (default) and 1.5v or 1.2v (pro grammable by twi), 70 ma linear low drop out regulator with high psrr and low noise. ldo4: 1.8v, 2ma linear low drop out regulator with very low quiescent current, +/- 100 mv adjustable. main supply rail from 2.8v to 5.5v independent auxiliary supply for ldo4 backup section, 2.8v to 5.5v internal state machine for startu p and delayed reset generation additional extern al reset input two wire interface for independent power up/power down and output voltage programming for each ldo. ldos voltage customization possible on request available in 3 x 3 x 0.9 mm 16-pin qfn package applications: gps modules, wl an devices, wireless modules. 1. description the AT73C237 is a four-channel power supply power management unit (pmu) avail- able in a small outline qfn 3 x 3mm package. it is a fully integrated, attractively priced, combined power management device for wireless modules, gps and wlan devices. it integrates 4x linear low drop out regulators, three of which (ldo1, 2, 3) provide high-accuracy rf performance and 1x (ldo4) with very low quiescent cur- rent, that can be supplied by an external backup battery (vdd4) on a separate rail. an internal low power bandgap (lpbg) requiring no external capacitor for decoupling, is used as reference voltage for ldo4 and starts when vdd4 is present. ldo4 regu- lates its output voltage with extremely low quiescent current, maximizing the lifetime of the backup battery. an internal state machine manages the startup of the other ldos. an economic high precision bandgap (hpbg) provides highly accurate, low noise voltage reference to ldos 1, 2, 3 while operating in switching mode to optimize the quiescent current. the AT73C237 features a two-wire interfac e (twi) to increase the efficiency of the system by disabling individually each ldo when not needed. power management and analog companions (pmaac) AT73C237 4-channel power management for wireless modules 6362a?pmaac?01-jul-08
2 6362a?pmaac?01-jul-08 AT73C237 2. block diagram figure 2-1. AT73C237 functional block diagram ldo1 2.75v/70ma por rcosc vdd1 (13) vo1 (14) level shifters xresin (1) xreso (4) twck (11) twd (12) gndd (6) twi interface and digital state machine ldo2 1.80v/70ma vdd2 (9) vo2 (10) ldo3 1.80v/70ma vdd3 (3) vo3 (2) 2.70v supply monitor ldo4 1.80v/2ma vdd4 (7) vo4 (5) low power bandgap reference lpbg main bandgap reference hvbg ldo gnda (15) vbg (16) vzap (8) trim
3 6362a?pmaac?01-jul-08 AT73C237 3. pin description note: 1. connect to ground (via an internal pull-down) 2. connected to vdd1, 2 or 3 on AT73C237. 3. connected to vdd1, 2 or 3 on AT73C237. 4. vdd1, 2, 3 should have the same input voltage. table 3-1. pin description pin name i/o pin number type function xresin input 1 digital reset in pin vo3 output 2 analog ldo3 output voltage vdd3 input 3 power ldo3 input voltage xreso output 4 digital reset out pin vo4 output 5 analog ldo4 output voltage gndd gnd 6 power digital ground vdd4 input 7 power ldo4 input voltage vzap (1) input 8 digital reserved for manufacturing purposes. vdd2 input 9 power ldo2 input voltage vo2 output 10 analog ldo2 output voltage twck (2) input 11 digital twi input clock or ldo1,2,3 enable at logic ?1?, disable at ?0? twd (3) input 12 digital twi input/output or tied to vdd vdd1 (4) input 13 power ldo1 input voltage vo1 output 14 analog ldo1 output voltage gnda/avss gnd/input 15 analog analog ground and esd ground vbg output 16 analog voltage reference for analog cells
4 6362a?pmaac?01-jul-08 AT73C237 4. application block diagram figure 4-1. AT73C237 application block diagram with gps module typical application components design schematic reference pin description c1 vo1 2.2 f 15% ceramic capacitor, x5r, 0402, 6.3v murata ? : grm155r60j225me15 tdk: c1005x5r0j225mt c2 vo2 c3 vo3 c4 vo4 c5 vdd1 1 f 15% ceramic capacitor, x5r, 0402, 6.3v murata: grm155r60j105ke19 tdk: c1005x5r0j105kt c6 vdd2 c7 vdd3 c8 vdd4 c9 vbg 100 nf 15% ceramic capacitor, x5r, 0402, 10v murata: grm155r61a104ka01 tdk: c1005x5r1c104kt d1, d2 on-semiconductor ? : bas70-04lt1 AT73C237 vzap (8) vdd4 (7) gndd (6) vo4 (5) xreso (4) vdd2 (9) vdd3 (3) vo2 (10) vo3 (2) twck (11) xresin (1) twd (12) vdd1 (13) vo1 (14) gnda (15) vbg (16) tx rx j 2 : "off" for 237 j 1 : "on" for 237 c 5 c 9 c 3 core and ios c 7 c 4 c 8 c 6 c 2 c 1 li-ion battery 3.0v to 4.2v 3v back up coin-cell d 2 d 1 gps baseband eg: panasonic cr1025 twi
5 6362a?pmaac?01-jul-08 AT73C237 5. electrical characteristics 5.1 absolute maximum ratings 5.2 recommended o perating conditions table 5-1. absolute maximum ratings operating temperature (industrial)..................-40 c to + 85 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or ot her conditions beyond those indicated in the operational se ctions of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reli- ability. storage temperature........................................-55c to + 150c power supply input on v dd .................................-0.3v to + 5.5v digital i/o input voltage...................................... -0.3v to + 5.5v all other pins.......................................................-0.3v to + 5.5v esd (all pins).......................................................................2 kv table 5-2. recommended operating conditions parameter condition min max units operating temperature -40 85 c power supply input v dd1 , v dd2 , v dd3 , v dd4 2.8 5.5 v
6 6362a?pmaac?01-jul-08 AT73C237 5.3 quiescent current in di fferent operating modes table 5-3. quiescent current in different operating modes modes conditions quiescent [a] typ max mode0 vdd4 not present, chip disabled, all vdds quiescent current 00.1 mode1 vdd4 present, vdd3 not present (typical mode with back-up battery on vdd4) ldo4 lpbg por hpbg in switching mode 12 18 mode2 vdd4 present, vdd3 present ldo4 lpbg por supply monitor registers oscillator state machine hpbg ldo1 ldo2 ldo3 800 1000
7 6362a?pmaac?01-jul-08 AT73C237 6. startup procedure 6.1 at vdd4 rising lpbg, ldo4, rcosc start up por connected to ldo4 output vo4 resets the state machine and enables: ? the reading of the internal fuses (trim cell in the application diagram) in order to set up the programmed output voltage of ldo1, ldo2, ldo3, and the correct reference voltage and oscillation frequency ? the two wire interface ? then under control of the state machine: a. hpbg is turned on b. after 4 ms, the supply monitor on vdd3 is turned on. c. if vdd3 is present and greater than 2.7v, ldo1, 2, 3 are turned on. during ldo regulator startup vdd3 voltage is checked. d. then xreso is kept grounded for 180 ms, and set to ?1? for 1ms before following xresin. during that state vdd3 voltage is monitored and if lower than 2.6v, ldo regulators 1, 2 and 3 are stopped and xreso grounded. both xresin and the supply monitor on vdd3 are debounced at rising and falling edges for two 10 khz clock cycles. the debounce time is typically between 100 s and 200 s. timings are defined 40%. 6.2 at vdd3 falling the supply monitor generates a shut down control signal when vdd3 reaches 2.6v the state machine sets xreso to logic ?0?. the state machine switches off ldo1, ldo2, ldo3. hpbg is kept enabled in order to assure a fast new startup of the ldos.
8 6362a?pmaac?01-jul-08 AT73C237 figure 6-1. startup procedure start wait xms load fuse regs hpbg en=0 vdd3 monitor en=0 ldo3 en=0 ldo2 en=0 ldo1 en=0 xreso=0 vdd4 is present rcosc running por reset signal goes to low hpbg hpbg en=1 vdd3 monitor en=0 ldo3 en=0 ldo2 en=0 ldo1 en=0 xreso=0 wait 4ms 32 clock pulses 100s (1 clock pulse) test vdd3 hpbg en=1 vdd3 monitor en=1 ldo3 en=0 ldo2 en=0 ldo1 en=0 xreso=0 vdd3 > 2.7v start ldos wait 1ms vdd3 < 2.6v hpbg en=1 vdd3 monitor en=1 ldo3 en=1 ldo2 en=1 ldo1 en=1 xreso=1 wait 180ms reset gen. hpbg en=1 vdd3 monitor en=1 ldo3 en=1 ldo2 en=1 ldo1 en=1 xreso=1 wait 1ms vdd3 < 2.6v wait 1ms ext. reset hpbg en=1 vdd3 monitor en=1 ldo3 en=1 ldo2 en=1 ldo1 en=1 xreso=xresin wait 1ms vdd3 < 2.6v
9 6362a?pmaac?01-jul-08 AT73C237 7. timing diagram figure 7-1. AT73C237 timings table 7-1. timing parameters parameter signal constraint min max units t ini guard time 100 sec t bg hpbg hpbg startup time 2 msec t ensm supply monitor supply monitor enable 4 msec t start1 v o1, v o2, v o3 35sec t start2 v o1, v o2, v o3 ldo1,2,3 startup time 10 100 sec t resgen xreso 100 500 msec t delay 1 msec vin 2.7v vbat ldo4 por 1.5v rcosc hpbg t ini t bg supply monitor t ini enabled ldo1,2,3 t start2 t start1 xresin t delay xreso t resgen t ensm
10 6362a?pmaac?01-jul-08 AT73C237 8. electrical specification 8.1 ldo1 table 8-1. ldo1 parametric table symbol parameter comments min typ max units v dd1 operating supply voltage switching regulated 2.8 3.3 5.5 v v o1 output voltage default 2.70 2.75 2.8 v programmed 1.75 1.80 1.85 i 1 load current with at least 300mv drop out 100 ma with at least 200mv drop out 70 i qc quiescent current 250 300 a i sc shutdown current hiz output 1 a i sh short circuit current 350 ma t r startup time 1 10 100 sec ? v dc line regulation static from vdd=3.0v to 3.6v 5 mv ? v dc load regulation static from 10% to 100% i 1 30 mv from 0 to 100% i 1 40 pssr power supply rejection ratio sine wave, 100 khz frequency, 3.3v mean +/- 100 m v pp 65 db sine wave, 10 khz frequency, 3.3v mean +/- 100 m v pp 60 db sine wave, 1 khz frequency, 3.3v mean +/- 100 m v pp 45 db ? v out startup overshoot 100 mv v nt total output noise 10 hz - 100 khz 35 100 v rms table 8-2. ldo1 external components schematic reference description c 1 (input capacitor) 2.2f 15% ceramic capacitor, x5r, 0402, 6.3v murata: grm155r60j225me15 tdk: c1005x5r0j225mt c 5 (output capacitor) 1f 15% ceramic capacitor, x5r, 0402, 6.3v murata: grm155r60j105ke19 tdk: c1005x5r0j105kt
11 6362a?pmaac?01-jul-08 AT73C237 figure 8-1. ldo load regulation figure 8-2. ldo1 output noise load regulation: vout1 = 2.75v 2.71 2.72 2.73 2.74 2.75 2.76 2.77 2.78 2.79 2.8 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 i load (ma) vout1 (v) vin=5.5v vin=2.8v vin=3.3v load regulation: vout1 = 1.8v 1.784 1.785 1.786 1.787 1.788 1.789 1.79 1.791 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 i load (ma) vout1 (v) vin=5.5v vin=3.3v vin=2.8v a: ch1 pwr spec x:1.001 khz y:775.467 nvrms 5hz 1.605khz avg: 30 100 uvrms 100 nvrms logmag 3 decades band:15.4997 uvrms a: ch1 pwr spec x:1 khz y:10.4272 uvrms 1khz 103.4khz avg: 30 100 uvrms 1 uvrms logmag 2 decades band:30.8786 uvrms
12 6362a?pmaac?01-jul-08 AT73C237 8.2 ldo2 table 8-3. ldo2 parametric table symbol parameter comments min typ max units v dd2 operating supply voltage switching regulated 2.8 3.3 5.5 v v o2 output voltage default 1.75 1.80 1.85 v programmed 1.45 1.50 1.55 i 2 load current with at least 300mv drop out 100 ma with at least 200mv drop out 70 i qc quiescent current 250 300 a i sc shutdown current hiz output 1 a i sh short circuit current 350 ma t r startup time 1 10 100 sec ? v dc line regulation static from vdd=3.0v to 3.6v 5 mv ? v dc load regulation static from 10% to 100% i 2 30 mv from 0 to 100% i 2 40 pssr power supply rejection ratio sine wave, 100 khz frequency, 3.3v mean +/- 100 m v pp 70 db sine wave, 10 khz frequency, 3.3v mean +/- 100 m v pp 65 db sine wave, 1 khz frequency, 3.3v mean +/- 100 m v pp 45 db ? v out startup overshoot 100 mv v nt total output noise 10 hz - 100 khz 25 50 v rms table 8-4. ldo2 external components schematic reference description c 2 (input capacitor) 2.2f 15% ceramic capacitor, x5r, 0402, 6.3v murata: grm155r60j225me15 tdk: c1005x5r0j225mt c 6 (output capacitor) 1f 15% ceramic capacitor, x5r, 0402, 6.3v murata: grm155r60j105ke19 tdk: c1005x5r0j105kt
13 6362a?pmaac?01-jul-08 AT73C237 figure 8-3. ldo2 load regulation figure 8-4. ldo2 output noise load regulation: vout2 = 1.5v 1.494 1.495 1.496 1.497 1.498 1.499 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 i load (ma) vout2 (v) load regulation: vout2 = 1.8v 1.7815 1.783 1.7845 1.786 1.7875 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 i load (ma) vout2 (v) vin=5.5v vin=3.3v vin=5.5v vin=2.8v vin=3.3v vin=2.8v a: ch1 pwr spec x:1.001 khz y:564.828 nvrms 5hz 1.605khz avg: 30 100 uvrms 100 nvrms logmag 3 decades band:10.1724 uvrms a: ch1 pwr spec x:1 khz y:5.0418 uvrms 1khz 103.4khz avg: 30 10 uvrms 1 uvrms logmag 1 decades band:19.7939 uvrms
14 6362a?pmaac?01-jul-08 AT73C237 8.3 ldo3 table 8-5. ldo3 parametric table symbol parameter comments min typ max units v dd3 operating supply voltage switching regulated 2.8 3.3 5.5 v v o3 output voltage default 1.75 1.80 1.85 v programmed 1.45 1.50 1.55 programmed 1.18 1.23 1.28 i 3 load current with at least 300mv drop out 100 ma with at least 200mv drop out 70 i qc quiescent current 250 300 a i sc shutdown current hiz output 1 a i sh short circuit current 350 ma t r startup time 1 10 100 sec ? v dc line regulation static from vdd=3.0v to 3.6v 5 mv ? v dc load regulation static from 10% to 100% i 3 30 mv from 0 to 100% i 3 40 pssr power supply rejection ratio sine wave, 100 khz frequency, 3.3v mean +/- 100 m v pp 70 db sine wave, 10 khz frequency, 3.3v mean +/- 100 m v pp 65 db sine wave, 1 khz frequency, 3.3v mean +/- 100 m v pp 45 db ? v out startup overshoot 100 mv v nt total output noise 10 hz - 100 khz 20 50 v rms table 8-6. ldo3 external components schematic reference description c 3 (input capacitor) 2.2f 15% ceramic capacitor, x5r, 0402, 6.3v murata: grm155r60j225me15 tdk: c1005x5r0j225mt c 7 (output capacitor) 1f 15% ceramic capacitor, x5r, 0402, 6.3v murata: grm155r60j105ke19 tdk: c1005x5r0j105kt
15 6362a?pmaac?01-jul-08 AT73C237 figure 8-5. ldo3 load regulation figure 8-6. ldo3 output noise load regulation: vout3 = 1.23v 1.2275 1.229 1.2305 1.232 1.2335 1.235 1.2365 1.238 1.2395 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 i load (ma) vout3 (v) load regulation: v out3 = 1.5v 1.4915 1.493 1.4945 1.496 1.4975 1.499 1.5005 1.502 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 i load (ma) vout3 (v) load regulation: vout3 = 1.8v 1.781 1.783 1.785 1.787 1.789 1.791 1.793 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 i load (ma) vout3 (v) vin=5.5v vin=2.8v vin=3.3v vin=5.5v vin=2.8v vin=3.3v vin=5.5v vin=3.3v vin=2.8v a: ch1 pwr spec x:1.001 khz y:604.928 nvrms 5hz 1.605khz avg: 30 100 uvrms 100 nvrms logmag 3 decades band:8.7275 uvrms a: ch1 pwr spec x:1 khz y:4.27822 uvrms 1khz 103.4khz avg: 30 10 uvrms 1 uvrms logmag 1 decades band:19.8695 uvrms
16 6362a?pmaac?01-jul-08 AT73C237 8.4 ldo4 table 8-7. ldo4 parametric table symbol parameter comments min typ max units v dd4 operating supply voltage switching regulated 2.8 3.3 5.5 v v o4 output voltage default 1.7 1.8 1.9 v i 4 load current 2ma tvo4 trimming range -80 0 80 mv i qc quiescent current 1 3 a i sc shutdown current hiz output 0.5 a t r startup time 1 10 100 sec ? v dc line regulation static 2.8v< vdd4 <5.5v 100 mv ? v dc load regulation static 0< i 4 <1.8ma 100 mv table 8-8. ldo4 external components schematic reference description c 4 (input capacitor) 2.2f 15% ceramic capacitor, x5r, 0402, 6.3v murata: grm155r60j225me15 tdk: c1005x5r0j225mt c 8 (output capacitor) 1f 15% ceramic capacitor, x5r, 0402, 6.3v murata: grm155r60j105ke19 tdk: c1005x5r0j105kt
17 6362a?pmaac?01-jul-08 AT73C237 8.5 high perform ance bandgap (hpbg) 8.6 low power bandgap (lpbg) 8.7 voltage monitor table 8-9. hpbg parametric table symbol parameter conditions min typ max units v i operating supply voltage backup battery or supercap 2.4 3.6 v v bg output voltage factory trimmed 1.231 v i sc shutdown current encore = en = 0, dcrun = 0 (1) 1 6 a i qc quiescent current not pulsed 300 a pulsed 30 t s startup time c 9 = 100 nf 1 2 ms v n output noise bw 10 hz to 100 khz 7 v rms table 8-10. external components schematic reference description c 9 (output capacitor) 100 nf 15% ceramic capacitor, x5r, 0402, 10v murata p/n: grm155r61a104ka01 tdk: c1005x5r1c104kt table 8-11. lpbg parametric table symbol parameter conditions min typ max unit v i operating supply voltage backup battery or supercap 2.8 5.5 v i qc quiescent current at v bat 3. =v 4 7.5 a t s startup time 50 100 s v lpbg bandgap voltage 1.15 1.2 1.25 v table 8-12. voltage monitor parametric table symbol parameter conditions min typ max unit i qc quiescent current 5 20 a v pon sm on threshold 2.7 2.72 v v poff sm on threshold 2.6 2.62 v
18 6362a?pmaac?01-jul-08 AT73C237 8.8 xresin 8.9 xreso 8.10 twck 8.11 twd table 8-13. xresin parametric table symbol parameter conditions limits unit min typ max v i input supply voltage range driven by cpu gpio v dd4 v driven by cpu open drain output hiz v connected to v dd4 when not used v dd4 v i ih high input current 5a i il low input current 50 a table 8-14. xreso parametric table symbol parameter conditions min typ max unit v i input supply voltage range v dd4 v v oh high output voltage 200 mv v ol low output voltage 150 mv table 8-15. twck parametric table symbol parameter conditions min typ max unit v i input supply voltage range v dd4 v i ih high input current 15 a i il low input current 13 a table 8-16. twd parametric table symbol parameter conditions min typ max unit v i input supply voltage range v dd4 v i ih high input current 20 a i il low input current 20 a v oh high output voltage 200 mv v ol low output voltage 150 mv
19 6362a?pmaac?01-jul-08 AT73C237 9. functional description the AT73C237 is a fully integrated, attractively priced, combined power management. it inte- grates the following power supplies channels. 9.1 ldo1 ldo1 is a 2.75v/70ma ldo, compatible with rf performances. ldo1 can work with supply from 3.0v up to 5.5v and needs at least 300 mv of minimum drop-out. this ldo is designed to supply the rf section of wireless devices, s howing high psrr up to 100 khz with very low noise on wide frequency bandwidth. ldo1 requires a 2.2 f output capacitor. additionally, 1.80v output voltages programming is possible via the twi serial interface. figure 9-1. ldo1 functional diagram v o1 v in v dd1 c 1 v bg av ss on1 overcurrent detection current reference sel1 gnda gnda vdd esd vouts
20 6362a?pmaac?01-jul-08 AT73C237 9.2 ldo2 ldo2 is a 1.80v/70ma ldo, compatible with rf performances. ldo2 can work with supply from 3.0v up to 5.5v and needs at least 300 mv of minimum drop-out. this ldo is designed to supply rf section of wireless devices, showing high psrr up to 100khz, very low noise on wide frequency bandwidth. ldo2 requires a 2.2 f output capacitor. additionally, 1.50v output voltages programming is possible via the twi serial interface. figure 9-2. ldo2 functional diagram v o2 v in v dd2 c 2 v bg av ss on2 overcurrent detection current reference sel2 gnda gnda vdd esd vouts
21 6362a?pmaac?01-jul-08 AT73C237 9.3 ldo3 ldo3 is a 1.80v/70ma ldo, compatible with rf performances (see electrical specifications for details). ldo3 can work with supply from 3.0v up to 5.5v and needs at least 300mv of minimum drop-out. this ldo is designed to supply rf se ction of wireless devices, showing high psrr up to 100 khz, low noise on wide frequency bandwidth. ldo3 requires a 2.2 f output capacitor. additionally, 1.50v or 1.20v output voltages programming is possible via the twi serial interface on AT73C237. figure 9-3. ldo3 functional diagram v o3 v in v dd3 c 3 v bg av ss on3 overcurrent detection current reference sel3<1:0> gnda gnda vdd esd vouts v inc
22 6362a?pmaac?01-jul-08 AT73C237 9.4 ldo4 ldo4 is a 1.80v/2ma ldo with very low quiescent current. ldo4 can work with supply from 2.8v up to 5.5v. ldo4 requires a 1 f output c apacitor. it needs at least 300 mv of minimum drop-out. ldo4 is always active once the pin vdd4 is supplied since it is used as internal refer- ence supply. the vdd4 rail is independent from the other input rails (vdd1, 2, 3), allowing ldo4 to be used to supply a real time clo ck from a separate backup battery, for example. figure 9-4. ldo4 functional diagram 9.5 high perform ance bandgap (hpbg) hpbg is a low power, low noise band gap circuit providing very accurate voltage reference to ldos that then can supply rf sections. hpbg operates in switching mode decreasing its cur- rent consumption. economic high performance bandgap is particularly interesting when rf ldos are in idle mode (output voltage provided with very low output current e.g. <1ma). hpbg is biased from an internal regulat or supplied by vdd4, thus it is not active when only vdd3 is present. hpbg requires at least external 100nf c apacitor to achieve very low noise/high accu- racy voltage reference. hpbg is trimmed to 1.231v during product test. 9.6 low power bandgap (lpbg) lpbg is a low power bandgap circuit used as re ference voltage for ldo4. lpbg starts up as soon as vdd4 is present and doesn't requ ire any external capacitor for decoupling. 9.7 reset generator a reset generator produces an output reset (rising from ?0? to ?1?), called xreso, at least 100 ms after the input reset state is activated. the input reset state can be produced by: vdd3 rising up, xresin not used or at ?1?. external signal rising up on xresin and vdd3 present. v o4 v in v dd4 c 4 v bg av ss en3 sel4 <1:0> gnda gnda vdd esd vouts v batc i bias trcore <1:0> v zap v zapc gnddc vcore
23 6362a?pmaac?01-jul-08 AT73C237 9.8 state machine an internal state machine supervises the start up of the regulators connected to vdd1, vdd2 and vdd3. the startup configuration is in the following order ldo3 then ldo1 then ldo2. a voltage must be present on vdd4 to supply ldo4. 9.9 oscillator an internal oscillator (rcosc) is used to generate th e internal master clock which synchronizes the state machine controlling the st art up of the ldos and hpbg. 9.10 power-on-reset a power-on-reset (por) monitors the output of ldo4 (vo4) and generates an internal signal to enable the trimming registers to be loade d for ldo1, ldo2, ldo3 output voltage program- ming, as well as for the referenc e voltages and internal oscillator trimming. this internal signal is released when vo4 is higher then 1.5v 300 mv. 9.11 supply monitor a supply monitor is set on vdd3 and generates an internal signal to enable state machine to startup the ldos and to generate the xreso sign al. the threshold has been set to 2.7v when rising up and 2.6v when falling down. 9.12 digital control on AT73C237, the pins twck, twd are respectively the clock and data lines of a true two-wire interface, allowing to activate and disable t he output voltage delivered by the regulators ldo1, ldo2, ldo3 and also to change their output voltage value.
24 6362a?pmaac?01-jul-08 AT73C237 9.13 two-wire interface (twi) protocol the two-wire interface interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds up to 400 kbits per second, based one a byte oriented transfer format. the twi is slave only and single byte access. the interface adds flexibility to the power s upply solution, enabling ldo regulators to be con- trolled depending on the instantaneous application requirements. the AT73C237 has the following 7-bit address:1001000. attempting to read data from register addresses not listed in this section results in 0xff being read out. twck is an input pin for the clock twd is an open-drain pin that drives or receives the serial data the data put on the twd line must be 8 bits long. data is transferred msb first. each byte must be followed by an acknowledgement. each transfer begins with a start condition and terminates with a stop condition. a high-to-low transition on twd while twck is high defines a start condition. a low-to-high transition on twd while twck is high defines a stop condition. figure 9-5. twi start/stop cycle figure 9-6. twi data cycle after the host initiates a start condition, it sends the 7-bit slave address defined above to notify the slave device. a read/write bit follows (read = 1, write = 0). the device acknowledges each received byte. the first byte sent after device address and r/w bit is the address of the device register the host wants to read or write. for a write operation the data follows the internal address for a read operation a repeated start condition needs to be generated followed by a read on the device. twd twck start stop twd twck start address r/w ack data ack data ack stop
25 6362a?pmaac?01-jul-08 AT73C237 figure 9-7. twd write operation figure 9-8. twd read operation s = start p = stop w = write r = read a = acknowledge n = not acknowledge addr = device address iaddr = internal address a iaddr a p data a s addr w twd a iaddr a s addr w s addr r a data np twd
26 6362a?pmaac?01-jul-08 AT73C237 10. registers 10.1 ldo control: ldo_ctrl (0x00) 10.2 ldo 1,2,3 trim : ldo_trim1 (0x08) table 10-1. registers address register description access reset value 000 ldo_ctrl ldo control read / write 0x0f 008 ldo_trim1 ldo 1,2,3 trim read / write 0x00 00a ldo_trim4 ldo4 trim read / write 0x00 76543210 - - - - onldo4 onldo3 onldo2 onldo1 table 10-2. ldo_ctrl (0x00) structure bit name description reset value 7:4 - not used - 3 onldo4 ldo4 enable (active high, hiz when off) 1 2 onldo3 ldo3 enable (active high, hiz when off) 1 1 onldo2 ldo2 enable (active high, hiz when off) 1 0 onldo1 ldo1 enable (active high, hiz when off) 1 76543210 ---sel1sel2sel3 - table 10-3. ldo_trim1 (0x08) structure bit name description reset value 7:5 - not used - 4 sel1 ldo1 output voltage select 0 3 sel2 ldo2 output voltage select 0 2:1 sel3 ldo3 output voltage select 00 0 - not used -
27 6362a?pmaac?01-jul-08 AT73C237 10.3 ldo 4 trim: ldo_trim4 (0x0a) table 10-4. ldo_trim1 (0x08) - output voltages selection sel1 vo1 sel2 vo2 sel3 vo3 0 2.75v 0 1.8v 00 1.8v 1 1.8v 1 1.5v 01 1.5v ----101.23v ----111.8 76543210 ----sel4 trcore1trcore0 table 10-5. ldo_trim1 (0x08) structure bit name description reset value 7:4 - not used - 3:2 sel4 ldo4 output voltage select 00 1:0 trcore ldo4 output voltage trimming 00 table 10-6. ldo_trim1 (0x08) - sel4 sel4 vo4 00 1.8v 01 - 10 - 11 - table 10-7. ldo_trim1 (0x08) - trcore trcore vo4 00 typ value (1.8v) 01 +80mv 10 -80mv 11 typ value (1.8v)
29 6362a?pmaac?01-jul-08 AT73C237 11. package information figure 11-1. mechanical package drawing for 16-lead quad flat no lead package
30 6362a?pmaac?01-jul-08 AT73C237 12. ordering information table 12-1. ordering information ordering code package package ty pe temperature operating range AT73C237 qfn 3x3 mm green 0c to +70c
31 6362a?pmaac?01-jul-08 AT73C237 13. revision history doc. rev comments change request ref. 6362a first issue
i 6362a?pmaac?01-jul-08 AT73C237 table of contents features ................ ................ .............. ............... .............. .............. ............ 1 1 description ............ .............. .............. ............... .............. .............. ............ 1 2 block diagram ............ ................ ................. ................ ................. ............ 2 3 pin description ......... ................ ................ ................. ................ ............... 3 4 application block diagram ..... ................ ................. ................ ............... 4 5 electrical characteristics ... .............. ............... .............. .............. ............ 5 5.1 absolute maximum ratings ...............................................................................5 5.2 recommended operating conditions ...............................................................5 5.3 quiescent current in different operating modes ..............................................6 6 startup procedure ...... ................ ................. ................ ................. ............ 7 6.1 at vdd4 rising ..................................................................................................7 6.2 at vdd3 falling .................................................................................................7 7 timing diagram ................. ................ ............... .............. .............. ............ 9 8 electrical specification ....... .............. ............... .............. .............. .......... 10 8.1 ldo1 ...............................................................................................................10 8.2 ldo2 ...............................................................................................................12 8.3 ldo3 ...............................................................................................................14 8.4 ldo4 ...............................................................................................................16 8.5 high performance bandgap (hpbg) ...............................................................17 8.6 low power bandgap (lpbg) ..........................................................................17 8.7 voltage monitor ...............................................................................................17 8.8 xresin ...........................................................................................................18 8.9 xreso ............................................................................................................18 8.10 twck ..............................................................................................................18 8.11 twd ................................................................................................................18 9 functional description ............ ................ ................. ................ ............. 19 9.1 ldo1 ...............................................................................................................19 9.2 ldo2 ...............................................................................................................20 9.3 ldo3 ...............................................................................................................21 9.4 ldo4 ...............................................................................................................22 9.5 high performance bandgap (hpbg) ...............................................................22
ii 6362a?pmaac?01-jul-08 AT73C237 9.6 low power bandgap (lpbg) ..........................................................................22 9.7 reset generator ..............................................................................................22 9.8 state machine ..................................................................................................23 9.9 oscillator ..........................................................................................................23 9.10 power-on-reset ..............................................................................................23 9.11 supply monitor .................................................................................................23 9.12 digital control ..................................................................................................23 9.13 two-wire interface (twi) protocol ...................................................................24 10 registers ......... ................. ................ ................. .............. .............. .......... 26 10.1 ldo control: ldo_ctrl (0x00) .....................................................................26 10.2 ldo 1,2,3 trim: ldo_trim1 (0x08) ................................................................26 10.3 ldo 4 trim: ldo_trim4 (0x0a) .....................................................................27 11 package information .............. .............. .............. .............. .............. ........ 29 12 ordering information .......... .............. ............... .............. .............. .......... 30 13 revision history ....... ................ ................ ................. ................ ............. 31 table of contents.......... ................. ................ ................. ................ ........... i
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